Data flow processor for multi-standard video codec

In multimedia digital video applications, international standards such as JPEG, MPEG, and H.261 are widely adopted. Many DSP architectures have been proposed to meet requirements on the digital video. In this paper, a static data flow architecture containing nine parallel processors is described. Each processor made with a specialized hardware engine such as DCT and quantizer operates asynchronously and independently on its own data presence. This proposed DSP is fabricated in a 0.8 /spl mu/m triple metal technology with 16/spl times/16 mm/sup 2/ die area over 1.5 million transistors. The peak computing capability over 1 billion operations per second can provide full programmability for any DCT based digital video compression standards.<
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