Improving cell libraries for synthesis

This paper examines the issues associated with building a cell library that will serve as the target for an automated synthesis tool and particularly focuses on cell library modifications that will improve the speed of a circuit. A number of library modifications are suggested here, and an experimental method for evaluating their effectiveness is described. This method is then used to quantify the importance of each modification as clearly as possible. The conclusion of this work is that relatively simple modifications in a cell library can lead to 20-30% improvements in final circuit speed, and that the principles motivating these modifications are not embodied in the cell sets of most commercial ASIC libraries.<
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