Architectures for a real time classification processor

We present the design of a real time parallel processor for classification adapted to image processing. We propose a geometric classification method by stress polytope training, allowing the use of a large number of parameters and ensuring a high decision speed. This classification operator has been integrated in the form of a full custom circuit developed in a CMOS 1.2 /spl mu/m process (area 29 mm/sup 2/). This powerful processor is able to classify a point in less than 100 ns. A comparison with a standard cell and an FPGA implementation (Xilinx XC4005) is made: it is shown that taking into account the reprogramming facilities of the SRAM based FPGAs, it is possible to implement a flexible reconfigurable classifier in a field programmable gate array.<
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