A programmable digital signal processor for service adaptive access

A programmable 24-bit RISC-based Digital Signal Processor with oversampled ADC and DAC has been designed in 1.2 /spl mu/m CMOS for use in a service adaptive subscriber loop interface. The processor has an instruction rate of 20.48 MHz and can perform most of the signal processing requirements for many services ranging from POTS to ISDN-U.<
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