Generating the optimal graph representations from the instruction set tables of circuits

In existing VLSI high-level synthesis systems, designs usually start from a hardware description language with structural information (such as structured VHDL, ISPS and HardwareC) or graph representations (such as data dependency graphs or control/data flow graphs). However, in most cases, such structured representations already "limit" or "fix" the design space and easily result in unsatisfactory implementations. In this paper a novel transformation technique is proposed to generate an optimal graph representation with structural information for the given instruction set table of a target design which does not contain any structural information and allow maximum flexibility in optimization. We first reorder and partition a given instruction set table, then a graph construction procedure is performed to extract and transform the maximal common operation sets. Finally, the local and global tuning transformations are performed to refine the graph representation. Experimental results show that performing our algorithm to generate the optimal graph representations before starting high-level synthesis tasks indeed produces much better final synthesized implementations.<
>