Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation

A fundamental limit of CMOS supply-voltage (V/sub CC/) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V/sub T/). Based on the data extracted from a sub-0.5 /spl mu/m logic technology, the variation of ring-oscillator propagation-delay (T/sub PD/) significantly increases as V/sub CC/ is scaled down towards the MOSFET V/sub T/ (Fig. 1). An empirical power-law relationship was then derived to describe the scattering of circuit speed (/spl Delta/T/sub PD/) as a function of MOSFET V/sub T/ variation(/spl Delta/V/sub T/) and (V/sub CC/-V/sub T/). Agreement between the model and the experimental data was established for V/sub CC/ values from 4.0 V to 0.9 V. This fundamental limit of CMOS V/sub CC/ scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable equipment and battery based systems.<
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