Component level yield/cost model for predicting VLSI manufacturability on designs using mixed technologies, circuitry, and redundancy

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar and BiCMOS process flows from low cost DIPs and QFPs to more complex PGAs and flip chip package solutions. This paper will discuss how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into affect variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost.<
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