I/sub DDQ/ testing on a custom automotive IC

This paper presents the impact of quiescent current (I/sub DDQ/) test on the fallout of a CMOS custom automotive IC designed to perform I/sub DDQ/ tests, I/sub DDQ/ patterns developed for this IC, together with the fault-graded patterns, achieved significantly higher fault coverage compared to the conventional Single Stuck-at-Fault (SAF) approach alone. We will show how the IC was designed to accommodate I/sub DDQ/ testing, how the I/sub DDQ/ faults were targeted and detected and analyze how it contributed to the reliability of the part. Setting the limits for the quiescent current and the impact of a voltage screen on these tests have also been presented.<
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