0.5 micron low-power BiCMOS gate array for B-ISDN 622 Mb/s user-network interface

A 0.5 micron low power BiCMOS gate array for B-ISDN 622 Mb/s User-Network Interface (UNI) is described. The gate array provides both 3k-gate ECL master array and 500 K-gate CMOS master array. It also offers ECL/TTL/CMOS mixed-level interface with dual power supply scheme (+3.3 V/-2 V) with low power consumption. The new ECL I/O buffers suitable to this scheme consume the power of 10 mW and 20 mW, respectively. A MUX/DEMUX on the ECL master array has been achieved with the power consumption 130 mW using LCML series-gates operating at the power supply of +3.3 V. The gate array is capable of realizing 4 pairs of 622 Mb/s UNI on a single chip with the power consumption of 4.3 W.<
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