A monolithic 625 Mb/s data recovery circuit in 1.2 /spl mu/m CMOS

This paper presents a technique and circuitry for recovering high speed data using a novel matched delay sampler. By simultaneously propagating the data and a slow clock through two different delay taps, the sampler achieves a very fine sampling resolution which is mainly limited by the delay difference between data and clock. Thus it is capable of oversampling data signals and greatly enhances the possibility of very high rate data recovery. This circuitry has been designed in MOSIS 1.2 /spl mu/m CMOS technology with an area of 10.8 mm/sup 2/. Simulation shows it is capable of taking 625 Mb/s (SONET-OC12) input data and makes a 1:4 demultiplexing of the data into four 156.25 Mb/s output streams. In the processing of data recovery, the slow clock phase tracks with the input data based on values extracted from the digital phase control circuit.<
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