A CMOS quaternary latch

A CMOS current-mode quaternary threshold logic latch circuit is proposed. This circuit accepts and requantizes quaternary logical currents during a setup clock mode and latches the input value during the hold clock mode. Using logical current increments of 10 mu A, the quaternary latch has been simulated to have a worst-case, three-logical-level transition, total setup and hold time of about 40 ns, and a single-level transition total setup and hold time of about 10 ns.<
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