An optimized compensation strategy for two-stage CMOS op amps

An optimized compensation strategy for two-stage Miller-compensated CMOS operational amplifiers is presented. The output conductance of the buffer which avoids the right half-plane zero is profitably used to achieve a pole-zero compensation. Indeed, thanks to a proper choice of the buffer transconductance, the compensation for the pole due to the load capacitor is reached, thus providing better frequency performance.<
>