Electromigration-induced integration limits on the future ULSI's and the beneficial effects of lower operation temperatures

In recent logic ULSI's, the problem of device integration density has tended to be dominated by interconnection-related issues rather than transistor-related ones. In seeking to establish an analytical model, this paper describes the limit on integration density caused by electromigration (EM) tolerance. In our model, all signal lines within a logic block are assumed to be local interconnections and to be the predominant factor in integration density. Also in our model, integration density is approximated to be inversely proportional to the average width of signal lines, which can be derived from their width distribution. The width distribution of EM-limited interconnections is connected to the gate width distribution of their corresponding driving transistors. The relation between the two distributions is derived by incorporating an expanded EM model that treats currents in signal lines as bi-directional periodic pulses. Scaling theory is also incorporated to investigate the future trend in integration density in terms of the MOSFET gate length. Calculated results predict that EM tolerance could become a significant restraining factor on the trend toward increasing integration density when MOSFET gate lengths are scaled down to the quarter-micron range. This constraint is found to disappear at moderately lower operation temperatures.<
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