A fast VLSI-efficient self-routing permutation network

A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2/spl times/4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log/sup 2/ N) gate-delay and uses O(N/sup 2/) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.<
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