Electrical characteristics of scaled CMOSFET's with source/drain regions fabricated by 7/spl deg/ and 0/spl deg/ tilt-angle implantations

The differences of electrical characteristics in trench-isolated n-well CMOSFET's with LDD- and EPS-regions fabricated by 7/spl deg/ and 0/spl deg/ tilt-angle phosphorous implantations are measured and qualitatively explained. The CMOSFET's have channel lengths ranging from 5 to 0.4 /spl mu/m and a channel width of 10 /spl mu/m. The differences in impurity profiles due to the channeling ions by 0/spl deg/-implantation cause the clear changes in the punchthrough-current characteristics and the substrate bias-voltage dependences of threshold voltages for both n- and p-MOSFET's. Meanwhile n- and p-MOSFET's fabricated by 7/spl deg/ and 0/spl deg/ implantations show nearly the same characteristics of threshold voltages and subthreshold swings which are almost determined by the impurity profiles in each channel region because the impurity profiles are scarcely affected by the channeling ions.<
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