Integration of two different gate oxide thicknesses in a 0.6-/spl mu/m dual voltage mixed signal CMOS process

An approach for integrating 3.3 V and 5.0 V transistors with two different gate oxide thickness layers, which eliminates the compromise between the transistor performance and reliability of the gate oxide layers, is described. The approach is robust, since gate oxide layers do not come in contact with photoresists, and relatively cost-effective in that it adds only two coarse masking steps. This approach has been demonstrated by integrating 16.5-nm 5.0 V and 10-nm 3.3 V gate oxide layers in a 0.6-/spl mu/m mixed signal CMOS process, and demonstrating good 3.3 V and 5.0 V transistor characteristics.<
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