Design and performance analysis of an output-buffering ATM switch with complexity of O(Nlog/sub 2/N)

Despite their excellent performance, most existing output buffering ATM switches suffer from high implementation complexity. A deflection-routing ATM switch that achieves output buffering is described. The switch is based on multi-layering of single-stage interconnection networks. An analytical model for the performance evaluation of the switch is developed. It is shown that for arbitrary small cell loss probabilities, the complexity of the switch is of O(log/sub 2/N). Furthermore, the proposed switch is fair and preserves cell-sequencing. The switch is shown to compare well with some known ATM switch architectures.<
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