System and performance design of the ATM node UT-XC

A large debate is going on around the possible use of the ATM network. The public TLC want a QoS guaranteed ATM network that can be used for the implementation of B-ISDN. The data communication operators ask for an ATM based backbone network, starting from interconnecting LANs. This forces the design of the ATM network nodes to be flexible and robust to face alternatives application scenarios. Taking care of this requirement, the system and performance design of the Italtel ATM node UT-XC are presented. The design of the node is based on a set of elementary building blocks, each realizing in hardware specific functionalities required for ATM switching. A high level of traffic performance is obtained using the internal speed advantage and cell distribution routing in the switching network. To rebuild the cell sequence integrity, a maximum delay equalization principle is used at node egress, which minimizes cell delay variation.<
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