A systematic layout-based method for the modeling of high-power HBT's using the scaling approach

A systematic scaling approach for the modeling of high-power/large-size HBT's is presented. This approach is based on: 1) identifying and characterizing the elementary cell, and 2) modeling the input/output interconnections using the device's physical layout. The proposed approach reduces the optimization problem for the large-size device to the easier fitting of the lumped equivalent circuit of the elementary cell. It is shown that there is a good agreement between the predicted results, using the developed model, and the available measurements for different bias points. Such a modeling approach is particularly appealing for high-power applications where the large-signal characterization of large-size devices becomes a difficult task, particularly for on-wafer devices.<
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