A massively parallel implementation of pattern classifiers on SIMD and MIMD architectures

Parallel multi-layer classifier architectures with an increasing hierarchical order have offered much flexibility in design to deal with a wide variety of properties. The model of pipeline processing is especially appropriate for realising such architectures. This has provided hierarchical classifiers a distinct advantage in real-time applications to cope with the important demand for high operating speed, in addition to a potentially better classification performance. An example application of a cascaded form of the BWS and FWS networks, both of which are representatives of the array memory based statistical classifier is described in this paper. As with most pipelined architectures, the complex interactions between successive processing layers of the cascaded network represent a major drawback, and they impose performance bottlenecks which challenge the use of a highly parallel realisation of the classifier. This paper describes an efficient data parallel implementation of the BWS-FWS. For completeness, a brief review of the multi-layer classifiers is first presented. The new algorithm for combining the BWS and FWS networks is described and implemented on two distributed memory processor arrays, the MasPar MP-1 and a network of transputers. An analysis of the performance obtained is also presented.<
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