Case study of ground plane inductance and implications for simulation

On a particular multilayer PGA, measurements of the inductance of a closed path (formed by routing the signal pin to the Vss pins through a copper ground plane) show about a 40% percent drop from the low-frequency asymptotic limit to the high-frequency limit. Electromagnetic simulation on a related problem shows similar trends. For the PGA tested, the high-frequency limit applies above about 30 MHz, and the low-frequency limit applies below about 100 kHz. These results indicate that for typical applications in digital packaging with clock rates in the tens of MHz range, electromagnetic as opposed to static simulation is needed for accurate inductance computation. A measurement on a typical Alloy 42 PGA pin and classic skin depth calculations show that electromagnetic simulation of inductance in the frequency band of current interest in packaging (1 MHz>