Concurrent packaging architecture design

Packaging constitutes one of the primary limits on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of physical packaging hierarchies is presented. Architecture, electrical performance, and energy management aspects of the system are included. The CAD system AUDIT implements this design methodology. The concurrent design capability has been illustrated using model systems derived from high speed Digital Equipment 3000/500 (Alpha) and IBM RS/6000 workstations. It is found that the choice of the packaging architecture as well as the impact of packaging on system performance is determined by the partitioning of the system.<
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