Fault simulation for delay faults

Methods to quantify the effectiveness of a delay test are presented. The notion of hazard insensitivity, which generalizes the notion of a robust delay test, is used to identify instances of test invalidation due too glitches. The delay fault-simulator is used to evaluate some built-in-self-test (BIST) schemes. The delay-fault simulator is built around a stuck-at fault simulator. This makes the overall fault-simulation process very efficient. Based on this, three measures of delay-fault coverage are defined. A BIST scheme for level-sensitive-scan design environment with improved delay-fault detection capabilities is proposed.<
>