Using hierarchy in macro cell test assembly

Test generation and assembly are investigated for hierarchical VLSI designs of modules with testable macro cells and an associated local controller. To create a testable (a) synchronous controller structure, the use of state cells is proposed. It is shown that a state-cell controller can be tested by reconfiguration into a token scanpath and that because of the direct correspondence between implementation and function, it permits accurate functional fault modeling and test-pattern generation. Such controllers also ease the assembly of the module test from the macro tests.<
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