Design of testable VLSI circuits with minimum area overhead

One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overhead minimization problem, for circuits into which BIST modifications are to be incorporated. Although the graph model does not account for a mixed type of BIST structure usage, it can be extended to include them at the cost of increased complexity.<
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