The reconfigurable ring of processors: fine-grained tree-structured computations

We study fine-grained parallel computation on a reconfigurable ring of processors (denoted by /spl Rscr//spl Rscr//spl Pscr/). The ring of processors is endowed with a very flexible reconfigurable bus. The bus has some number of lines, each having one-packet width, that can be configured to establish arbitrary point-to-point connections independently for each line. We assume that the /spl Rscr//spl Rscr//spl Pscr/s we study have been implemented so that the latency for transmitting messages is logarithmic in the number of processors the message passes over in transit. We present an algorithm that allows an N-processor /spl Rscr//spl Rscr//spl Pscr/ with w lines to perform the broadcast operation (and any "leveled tree-structured" computation like parallel prefix) in time at most (log/sup 2/ N/log w)+log N log log w. We prove that this algorithm's performance can be improved by at most a constant factor, both when the buswidth w is "small", so that the first term dominates, and when w is "large", so that the second term dominates. Further, we expose a fundamental, architecture-independent limitation imposed by the logarithmic communication latency model: we prove that for a broad range of parallel architectures, including any N-processor /spl Rscr//spl Rscr//spl Pscr/, any operation that requires one processor to receive information-directly or indirectly-from all other processors, requires time proportional to log N log log N.<
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