A data acquisition system for high rate chamber signals

A CAMAC system which provides delays, data compaction and readout of signals from high-rate proportional wire chambers is presented. A delay buffer containing a large, fast shift register constructed from high-speed ECL RAMs (emitter-coupled-logic random-access memories) is described in detail. This provides up to 5 mu s of delay with no deadtime for 32 binary data channels at a 20-ns sampling rate. A clock and gate distribution module synchronizes several delay modules for multichamber applications. A microprocessor is used to compact the data, thus reducing the volume before transmission to the main data acquisition system.<
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