A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

This paper describes a pair of delay-locked loops (one DLL for transmitting data, one for receiving) that satisfy the requirement for accurate timing (sub-100ps static phase error), even in the noisy environment (substrate and V/sub DD/) of DRAMs, to allow data transfer rates exceeding 500Mb/s/pin at 2.5V. While the application of delay-locked loops to the problem of host-slave synchronization is not new, the loop described in this paper solves several problems of conventional PLLs and DLLs, providing unlimited phase shift (modulo 2/spl pi/) without a VCO, enabling lock in under 200ns and good jitter performance at low supply voltages.<
>