Simulation of interface state generation effects in LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of an LDD MOSFET after hot carrier stress. The spatial distribution of interface states is calculated with a combined Monte Carlo and breaking silicon-hydrogen bond model. A 0.6 /spl mu/m LDD MOSFET was characterized to compare the simulation. A reduction of the substrate current at V/sub gspl cong/0.5 V/sub d/ in a stressed device was observed from both measurement and simulation. Our study reveals that the reduction is attributed to a distance between the maximum channel electric field and the generated interface states.<
>