CMOS VLSI design of 32/spl times/32 ATM switch using simple logic control

A 32/spl times/32 asynchronous transfer mode ATM switch consisting of interconnection network using 1/spl times/32 parallel expander circuits is presented to overcome the effect of internal path blocking. The CMOS VLSI architecture and the control unit consisting of serial shift registers and latches to keep the destination path open for the length of a packet, were designed using MAGIC software and simulated by IRSIM. The system performed well under a variety of input traffic patterns. As low as 5 ns delay was estimated by the 1/spl times/32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190 ns.<
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