A systolic computation scheme of time-delay neural networks

The basic idea developed in this paper is to study the viability of computing a TDNN algorithm in a systolic architecture. The main problem to adopt this kind of solution resides in the presence of the digital filter part of the NN algorithm. Such an irregularity requires the inclusion of some additional external hardware for the proper treatment of the data inputs to the pipeline. The external hardware proposed consists in two similar elements named distributor and collector. The complete algorithm is computed with the restriction of having available a pipeline of only four processors due to limitations in the area of silicon. To solve this problem, some partitioning and mapping techniques have been applied. Finally a brief discussion regarding performance aspects and conclusions are presented.<
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