Parametric delay and area models for adders

This paper derives delay and area estimates for the four major adder types: ripple carry, carry skip, carry select, and carry lookahead. The models take into consideration gate area variation and gate delay variation as a function of fan-in for various size AND and OR gates. In addition, layout considerations are also modeled. Equations for the time to the final sum and carry bit are derived for all the adders. In addition, equations for the area of the various adders are derived. Naive (or simple) models that do not take into account varying gate delays and area are provided for comparison. In conclusion, the models are applied to 16 bit adders for comparison and some suggestions are made for extending the models.<
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