A single chip high-speed M-to-B arbiter for multiple bus multiprocessor systems

An M-user B-server synchronous arbitration circuit is built on a single chip using NMOS technology. The VLSI layout is modular which consists of 3 basic blocks: Type-1, Type-2, and Type-3. For VLSI layout of each block, one has to perform a few interconnections in order to build M-user B-server arbiter on a single chip. We have justified this statement by building arbiters for 16-user 4-server, 4-user 2-server, and 8-user 2-server. This arbiter design on a single chip can considerably reduce the space for total arbitration circuit in any multiprocessor system. At the same time it is faster and consumes less power.<
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