Optimized sensing scheme of DRAMs

The half-V/sub cc/ sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V/sub cc/ generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line.<
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