A 14 ns 256 K*1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 mu m twin-tub, single-poly, double-metal technology on p/p/sup +/ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1*13.7 mu m/sup 2/ and a chip size of 3.9*9.5 mm/sup 2/ have been achieved.<
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