A new class of single event hard errors [DRAM cells]

Experimental results reported here indicate that heavy ions can cause hard errors in conventional one-transistor dynamic memory cells in addition to, as previously reported, four-transistor static cells. Analysis of this data reveals that the hard errors fail into two classes, one that is consistent with the expected single-ion dose mechanism and another that is clearly inconsistent. In particular, the new class of hard errors is separable from the dosed cells based on irradiation conditions and the data-loss time scale and direction. Further, this damage is not additive between ion hits, does not follow "effective" LET, and is quite resistant to annealing. As a result these hard errors would accumulate over long missions and assuming the damaged element is the access transistor, can be expected in other types of storage elements with similar transistors, e.g., static RAMs and microprocessor registers. Additionally, it was found that scaling increases the susceptibility for a given ion and lowers the ion threshold, although lowered bias mitigates the damage.<
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