Interface trap effect on gate induced drain leakage current in submicron N-MOSFET's

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5//spl mu/m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress. The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of /spl Delta/I/sub d/=A exp(-B/sub u//F) with a value of B/sub u/ of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.<
>