Inverter performance of 0.10 /spl mu/m CMOS operating at room temperature

The switching performance of 0.10 /spl mu/m CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 /spl mu/m gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 /spl mu/m CMOS. The switching performance of a 0.10 /spl mu/m ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 /spl mu/m ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance /spl rho//sub c/ is reduced to be less than 1/spl times/10/sup -7/ /spl Omega/ cm, further reduction of the gate overlap capacitance C/sub ov/ will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 /spl mu/m ground rule CMOS at room temperature.<
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