Large signal S parameter characterization of high power FET chips

Large signal S parameters have been measured up to 12 GHz on high power (6 W) 18 mm gate width FET chips. The unique feature of this method is its ability to measure both forward (S/sub 11/,S/sub 21/) as well as reverse (S/sub 12/,S/sub 22/) parameters while the chip is operating under high power levels. The paper describes an approach that deals with extremely low impedance levels (0.5 ohm or VSWRs >90:1). The test setup employs HP8510C configured with HP8511A test set and is controlled by software to set up a non 50 ohm impedance environment with full 2 port error correction capability. We present the locus of each S parameter of the chip as a function of its output power level ranging from 20 mW through 6 W.<
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