Automatic synthesis of FPGA channel architecture for routability and performance

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A channel architecture synthesis algorithm based on simulated annealing has been developed which enhances channel routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance. Excellent results have been obtained for a set of benchmark examples and industrial designs.<
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