On-chip TEC-QED ECC for ultra-large, single-chip memory systems

Soft errors resulted from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of the memory chip is to employ an on-chip code (ECC). This paper presents a triple-error correcting and quadruple-error detecting (TEC-QED) code that is capable of correcting three and detecting four soft errors simultaneously. Its design is based on odd-weight-column SEC-DED code in conjunction with the parity technique. Results show that timing overhead of less than 10 ns can be expected. The proposed code improves the mean time between failure (MTBF) by a factor of 250% when compared to DEC-DED APC and by a factor of 1300% when compared to any SEC code.<
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