Verifying SPICE results with hand calculations: handling common discrepancies

Students enrolled in a capstone design course on analog integrated circuits often encounter calculational difficulties when they attempt to verify key circuit parameters predicted by computer simulations using SPICE. Discrepancies between their hand calculations and SPICE values sometimes exceed 200%. This paper reviews some commonly encountered discrepancies, describes major causes of significant errors, and offers solutions that have been found to be effective. In particular, this paper discusses the impacts of variable transistor current gains (/spl beta//sub ac/ and /spl beta//sub dc/) on AC gain, input impedance, and quiescent point (Q point) determination. Since realistic computer simulations depend on realistic numerical models of active devices, SPICE parameters that realistically model BJTs, JFETs, and MOSFETs are given. The paper also discusses the large discrepancies typically found when calculating the output resistance (R/sub out/) of a Class AB push-pull stage operating near 0 VDC, the common mode rejection ratio (CMRR) of an actively loaded differential stage, and the frequency response of an internally compensated op amp circuit. Lastly, suggestions and recommendations for avoiding many calculational pitfalls also are presented.<
>