A high-performance SI memory cell

In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to a high accuracy cell with measured errors less than 200 ppm for input currents between 50 and 85 /spl mu/A. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.<
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