Future technology trends for static RAMS

SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance of interconnected limitations for circuit choices is discussed. CMOS and BiCMOS circuits are compared. Future packaging, chip size, electromigration, and signal-propagation constraints are treated. The major data-integrity issues (cell stability, data retention and soft-error) are examined for future scaled processes.<
>