Mechanism of hot electron trapping on PMOSFET with p/sup +/ polysilicon gate

The hot-carrier effects of a p/sup +/ polysilicon PMOSFET are compared with those of a surface-channel-type n/sup +/ polysilicon-gate PMOSFET. The p/sup +/ and the n/sup +/ PMOSFETs are fabricated with the same process except for doping of the gate polysilicon. MOS capacitors with p/sup +/ or n/sup +/ polysilicon gates are also prepared. The p/sup +/ FET has a highly boron doped SiO/sub 2/ film. An FN (Fowler-Nordheim)-tunneling constant-current stress test of MOS capacitors and the drain avalanche hot-carrier stress-time dependence of the threshold voltage shift indicate that electrons are distributed near the p/sup +/ polysilicon/SiO/sub 2/ interface, while they are located uniformly in the SiO/sub 2/ film of an n/sup +/ polysilicon gate MOSFET.<
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