A hardware scheduler for parallel processing in control applications

One approach to catering for the higher computational demands of modern digital control systems is to use parallel processing. Despite the many examples available which use this technique, it cannot be claimed that it is the natural choice of the control engineer for implementation. The premise for the work described in this paper is that parallel processing must be as transparent and convenient to the designer as a single processor solution, if it is to become an acceptable option. Problems such as deadlock, livelock, communication delays and network topologies contribute to the difficulty of parallel programming and should, as far as possible, be hidden from the user. The well-known processor farm paradigm is a step towards this goal because of its dynamic scheduling properties. However, control system applications generally involve processing relatively small amounts of data in short periods of time with a definite deadline which is more difficult to achieve than high average throughput on a large job. This paper describes a specialised hardware scheduler for a processor farm which minimises the overhead of scheduling multiple tasks to multiple processors. It also describes the harness software which allows the algorithm to be separately partitioned into tasks and incorporated as linked modules.<
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