Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 /spl mu/ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6/spl times/14.6 mm/sup 2/. The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA.<
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