Logic synthesis and verification of the CPU and caches of a mainframe system

This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits.<
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