A fragmented register architecture and test advisor for BIST

This paper describes two new developments in the implementation of quasi-exhaustive BIST. These are a new architecture, in which a conventional LFSR/MISR is broken down into three separate elements, and a CAD "test advisor" which provides a fast check of BIST DFT rules and informs the chip designer how to configure the registers and LFSRs within a design. These two new developments are closely interdependent and give a major increase in DFT productivity when implementing BIST.<
>