CMOS output buffers for megabit DRAMs

Output buffers for CMOS DRAMs are discussed and associated reliability risks and circuit design problems are shown. Concepts using true CMOS circuitry for output buffers are presented. Measurement results prove the feasibility of latch-up-free CMOS output structures, which have been implemented on a 4-Mb DRAM and use significantly less area than boosted NMOS concepts.<
>